Why dirty bit

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TEAM Today our team consists of 23 people. More about Bergen. Techopedia Terms. Connect with us. Sign up. Term of the Day. Best of Techopedia weekly. News and Special Offers occasional. Dirty Bit. Techopedia Explains Dirty Bit. What Does Dirty Bit Mean? A dirty bit is also known as a modified bit.

Techopedia Explains Dirty Bit For certain kinds of modifications, a computing system adds a dirty bit in memory. Cache Control Interface is used to control the L2 cache which includes managing tag store CACS !

CAWE ! TAG ! A cache write hit will set the dirty bit for the currently accessed cache line. Depending on the kind of DRAM modules being used, this signal may or may not need to be buffered externally. DRAM Interface is used to interface with the main memory.

This includes addressing and enabling DRAMs Depending on the kind of DRAM modules being used, these signals may or may not need to be buffered externally.

CAS ! Each DRAM bank has a bit data bus. The System Controller generates PEN internally if the corresponding register is programmed to enable parity. MA ! NVRAM is used for storing the system configuration information and is required for "plug and play" support.

UMA Arbiter Interface manages this sharing of the memory bus. This signal indicates to the GUI that it has been granted control of the memory bus. LA ! An external pull-up is required for normal operation. The PCI commands indicate the current cycle type, and the PCI byte enables indicate which byte lanes carry meaningful data.

FRAME is asserted to indicate the beginning and the duration of an access. It is used in conjunction with IRDY. It is used to determine if any device has responded to the current bus cycle, and to detect a target abort cycle.

Master abort termination results if no decode agent exists in the system, and no one asserts DEVSEL within a fixed number of clocks. AD ! The AD ! During power-up reset, the System Controller will drive the AD lines by default.

This bus also serves as a conduit for receiving address information during ISA master cycles. When PLOCK is asserted, non-exclusive transactions may proceed to an address that is not currently locked. Universal Serial Bus Interface is used for telecommunications, keyboards or audio peripherals. These commands inform the Data Buffer Controller about the current cycle type and enable it to perform the appropriate data steering, latching and direction controls. When asserted, this signal enables data to be put out on the MD bus.

When asserted, this signal enables data to be put out on the HD bus. DLE ! This input monitors ISA memory write operations. Cache control interface includes cache control logic , a line comparator , and an 8 bit tag comparator The disclosed embodiment L2 cache includes 8K lines 32 bytes per line ; therefore, tag store also includes 8K lines. The low order bits of the memory address are used to access the proper line in the tag store and the high order bits are stored as the tag.

In the disclosed embodiment, the tag is 8 bits. However, tag store is 9 bits wide so that each line in tag store can store a dirty bit. The system as depicted in FIG. Table 10 indicates which bits of the memory address to use as the tag for various L2 cache sizes.

Table 10 is just one example of how to divide the memory address bits, other examples are also within the spirit of the present invention. The choice of level 2 cache size is dependent on the system design. For illustrative purposes, FIG. Thus, HA !

The input to tag store includes the low order bits of the memory address HA ! The data port D ! Low order 8 bits D ! D ! The D ! The write enable for tag store is driven by cache control logic the signal TAGWE and serves as the tag write enable and the dirty bit write enable.

To write a tag or a dirty bit into the particular memory device used herein for tag store , TAGWE must be asserted for half a clock period prior to writing to tag store Subsequent to the half clock period needed for setup time, one clock is needed to write the new dirty bit or tag.

Thus, in the case where the writing of the dirty bit and tag can be skipped, the system can save 1. Tag comparator compares the high order bits from the memory address HA ! The output of tag comparator , HIT, is connected to cache control logic and indicates if there is a hit in the L2 cache.

Cache control logic sends the following 5 signals to line comparator HA ! Note that line comparator only receives a portion or subset of bits of the address HA. This is because only the address bits HA ! For example, addresses with the same HA !

Line comparator determines whether successive bus cycles are writes to the L2 cache at the same line location. If successive bus cycles are writes to different lines, the signal NO - - FNA is asserted and is sent to cache control logic The purpose of line comparator is to save clock cycles by not setting a dirty bit which has been recently set.

For example, suppose a first write to the L2 cache resulted in a hit causing the dirty bit to be set. If the next bus cycle is a write to the L2 cache at the same line as the previous cycle, then the exact same dirty data in the L2 cache is being overwritten. In that situation, cache control logic would know that dirty bit was set in the previous cache write and that there is no need to waste clock cycles setting the dirty bit a second time.

During a write to memory, system may check for a hit in the L2 cache. The low order bits of the memory address, HA ! The proper tag is accessed and sent to tag comparator and compared with the high order bits of the memory address HA !. If the tag matches the high order bits of the memory, then tag comparator communicates to cache control logic that there is a hit which indicates that the line of data which is the subject of the bus cycle is in the L2 cache.

If there was a hit then cache control logic 1 sends an address and write enable to the L2 cache SRAMs and 2 sets the corresponding dirty bit if address comparator asserts NO - - FNA. Setting the dirty bit includes driving the write enable pin of tag store e. If there was a miss in the L2 cache during a write cycle, the data is only written to main memory. During a read from memory, if the is an L1 cache miss, system will check for a hit in the L2 cache as described above.

If there is a hit, the data is read from the L2 cache and the tags and dirty bits are not changed. If there is a miss in the L2 cache, the data is fetched from main memory, delivered to CPU and stored in the L2 cache.

When storing the data in the L2 cache, cache control logic drives TAGWE , stores a new tag and resets the dirty bit. Before storing the new data and tag, cache control logic will check the dirty bit of the existing data in the L2 cache. If the dirty bit is set, the data must be written back to main memory before the new data is written to the L2 cache. Register stores the memory address of the previous bus cycle.

The input to register is the current 24 bit address, HA !. The clock input to register labeled GN is received from the output of inverter The input of inverter comes from the output of NOR gate Thus, register clocks in a new address at the end of every bus cycle. The output of register , LA ! Alternative embodiments include storing more than one previous address.

Register is used to make sure that address comparator fails to assert NO - - FNA only when successive bus cycles are both writes. Each of the current address bits A ! For example, bit 28 of the present address A28 is compared to bit 28 of the previous address LA28 by sending both signals to exclusive NOR gate If two corresponding address bits are the same, the output of the exclusive NOR gate is logic level one.

When the current address matches the previous or preceding address the output of all the exclusive NOR gates are logic level one. The inputs to NAND gate are the outputs from exclusive or gates , , and If two successive bus cycles are memory writes and their addresses are the same, the inputs to the NOR gates will be logic level zero and the outputs of the NOR gates will be logic level one.

The output of AND gate will be logic level one when the two addresses match. The signal IDX27 is a static signal originating from an internal register and is normally at logic zero. This signal will be equal to logic level zero when the current address is equal to the previous address.

The signal NO - - FNA is at logic level one when the current address is not equal to the previous address, IDX27 is logic level zero and the current bus cycle is a memory write cycle. Alternative designs for the line comparator and alternative definitions of the behavior of the NO - - FNA are also within the scope of the present invention as long as the system can determine when to avoid setting a dirty bit.

At the end of the second clock period cache control interface determines whether there is a hit or miss in the L2 cache. During a write cycle, regardless of whether there is a hit or miss, data is written to the L2 cache at the end of the second clock period.